Certain applications of electronic systems, such as military, aerospace, and high-reliability communications, require certain safeguards to ensure the integrity of the applications. One way to promote integrity of an application is to provide redundancy to ensure that the data for the application is correctly processed and retained. In the event of a failure of one circuit, the data of the redundant circuit may be used. Also, the detection of errors may also be required in these applications, even if the likelihood of such an occurrence is extremely low, in order to provide high accuracy. Furthermore, applications running in redundant systems require fast detection and correction of an error in order to minimize the impact upon the operation. Even a rare single event upset (SEU) must be detected so that appropriate system measures may be taken to ensure a very high uptime of the circuit. In certain circumstances, automatic correction of errors may also provide a significant advantage. For example, when processing real-time data, automatic correction of errors allows the operation of the circuit to continue without the need for a system reset. When employing a programmable logic device, error correction allows much faster system recovery time because the device does not need to be completely reconfigured, which may require many seconds of system downtime.
In other applications of electronic systems, the integrity of a system is maintained by providing separate integrated circuits for portions of the system. For example, in an encryption system, non-encrypted signals, often called red signal, must be isolated from a circuit providing access to encrypted signals, often called black signals. That is, careful segregation of signals is required in cryptographic systems that contain sensitive or classified plaintext information (i.e. red signals) and encrypted information, or ciphertext (i.e. black signals).
One class of integrated circuits which may be used to implement circuits requiring the integrity of data to be maintained is a programmable logic device (PLD). A PLD is designed to be user-programmable so that users may implement logic designs of their choices. Programmable logic circuits of a PLD comprise gates which are configurable by a user of the circuit to implement a circuit design of the user. One type of PLD is the Complex Programmable Logic Device (CPLD), which comprises two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose.
A PLD comprises circuit elements formed in a substrate and a plurality of metal layers coupling the circuit elements. The metal layers may comprise metal layers for connecting elements of a functional block, while other layers are used for connecting the various functional blocks. For example, the first five layers may comprise local routing conductors used for connecting circuit elements of the various functional blocks, such as memory elements or CLBs of a programmable logic device, while the upper six layers may comprise the interconnect circuits (i.e. conductors for connecting the various functional blocks). The even layers of the interconnect circuits may be used to route signals in a longitudinal direction, while the odd layers may be used to route signals in a lateral direction. The length of a conductor of the interconnect circuits may be defined by the number of conductor segments coupled between a pair of programmable interconnect points (PIPs) which enable local routing. Relatively short conductors (e.g. “double lines” comprising two segments between PIPs) may be included in a first pair of horizontal and vertical metal layers. Similarly, “hex lines” comprising six segments coupled between PIPs may be formed on another pair of horizontal and vertical metal layers. Finally, long conductors may be formed on another pair of horizontal and vertical metal layers. The long conductors may extend between the edges of the integrated circuit, for example. Alternatively, in larger programmable logic devices having a large number of columns, such as 150 columns, for example, long lines may extend a smaller number of columns, such as 32 columns.
PLDs also have different “modes” depending on the operations being performed on them. A specific protocol allows a programmable logic device to enter into the appropriate mode. Typical PLDs have internal blocks of configuration memory which specify how each of the programmable cells will emulate the user's logic. During a “program” mode, a configuration bitstream is provided to non-volatile memory, such as a read-only memory (ROM), either external or internal to the programmable logic device. Each address is typically accessed by specifying its row and column addresses. During system power up of a “startup” mode, the configuration bits are successively loaded from the non-volatile memory into static random access memory (SRAM) configuration latches of a configuration logic block. At the end of this start-up phase, the PLD is now specialized to the user's design, and the PLD enters into “user” mode as part of its normal operation.
In order for the PLD to function properly, it is necessary that the data loaded into a memory is not corrupted. Data in a PLD may be corrupted for a variety of reasons. For example, there may be a latent defect in the device. The device may also be affected by a single event upset (SEU), such as a cosmic ray striking a storage element of the device. Finally, the device may be subjected to an adversarial attack, such as an attack by a third party attempting to intercept data. For example, an unauthorized third party may attempt to access decrypted data in a data encryption system. However, because of the nature of the interconnect circuits of a programmable logic device, a single conventional programmable logic device does not provide adequate isolation for circuits requiring data integrity, such as redundant circuits or circuits requiring strict isolation such as encryption circuits.
Accordingly, there is a need for an improved circuit for and method of implementing a plurality of circuits on a programmable logic device.